Modern integrated circuits are made up of literally millions of active devices such as transistors and capacitors. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. A passivation layer is also included for protecting underlying layers from moisture, contamination, or other conditions that can potentially degrade or damage the integrated circuit. Wafer level chip scale packaging (WLCSP) is currently widely used for its low cost and relatively simple processes. In a typical WLCSP, interconnect structures are formed on metallization layers, followed by the formation of under-bump metallurgy (UBM), and the mounting of solder balls. In a post passivation interconnect (“PPI”) process, contact pads and other conductors are fabricated on top of the passivation layer and connected to the contact regions of the integrated circuit. The PPI scheme can be used to re-route the connections to integrated circuit to facilitate contact to the package. Conventionally, silicon nitride or polyimide is provided for preventing the PPI made of Cu from oxidation, but an additional patterning step (e.g., an etching process for pattering silicon nitride layer or an exposure step for pattering the polyimide layer) is necessary to allow subsequent bump processes. The Q-time between the Cu plating to the polyimide coating process is a concern since there is no deoxidizing step in the polyimide process.